1. Field of the Invention
The present invention is related to a majority circuit, especially suitable for data transfer adopting a data inversion technology.
2. Description of the Related Art
Memory devices which output many-bit data, such as 16-bit and 32-bit dynamic random access memories (DRAM), often suffer from switching noise caused by data flipping (or switching) during data transfer. An increase in the number of flipped data bits enhances generation of switching noises, and thus transferring many-bit data often generates considerable switching noise.
A data inversion technology is promising for reducing switching noises in memory devices. This technology alters the pattern of output data to minimize data flipping during read operations. An exemplary data inversion technology involves inverting all the data bits within the output data that will be outputted at the current clock cycle, when the majority of the data bits to be outputted at the current clock cycle are expected to be flip compared to the corresponding data bits outputted at the previous clock cycle.
The data inversion technology decreases the number of flipped data bits within the output data down to half or less of the number of all the data bits, and thereby effectively reduces switching noises. For example, the adoption of the data inversion technology to a 32-bit DRAM reduces the switching noise therefrom to be identical to that from a 16-bit DRAM which does not adopt the data inversion technology.
A memory device adopting a data inversion technology requires a majority circuit which determines whether the majority of the data bits that will be outputted at the current clock cycle will be flip compared to the corresponding data bits at the previous clock cycle.
FIG. 1 shows a typical 8-input majority circuit. The conventional majority circuit includes an OR gate 101, and a plurality of AND gates 102 connected to the OR gate 101. The number of the inputs of the OR gate 101 and the AND gates 102 is based on the number of the different combinations of the inputs of the majority circuit. The 8-input majority circuit requires the OR gate 101 to have as many as 70 inputs, the number of the inputs of the OR gate 101 being determined by 8C4 (=70). Correspondingly, the majority circuit requires as many as 70 AND gates 102.
The conventional majority circuit suffers from a problem that an increase in the number of the inputs of the majority circuit increasingly enlarges the size of the majority circuit. The enlargement of the size of the majority circuit undesirably increases cost of the memory devices.
Various technologies are disclosed for reducing the size of a majority circuit. A size-reduced majority operation circuitry is disclosed in Japanese Open Laid Patent Application (Jp-A 2000-148605). The majority operation circuitry includes a plurality of m-input majority circuits, and an s-input majority circuit connected to the outputs of the m-input majority circuits, m being an integer equal to or more than 2, and s being the number of the m-input majority circuits. This architecture achieves a fast small input majority circuit.
Other size-reduced majority circuits are disclosed in Japanese Open Laid Patent Application (Jp-A Heisei 8-204562, Jp-A Heisei 9-64743, and Jp-A Heisei 9-130250). These size-reduced majority circuits include a plurality of switching elements respectively connected to a plurality of data inputs, a plurality of capacitors respectively connected to the first switching elements, and a sense amplifier connected to the capacitors. The output of the sense amplifier represents the result of a majority operation on the data inputs.
A D/A converter circuitry which may be related to the present invention is disclosed in Japanese Open Laid Patent Application (Jp-A 2002-94380). The D/A converter circuitry includes a plurality of D/A converters, a majority circuit, a selector connected to the outputs of the D/A converters. The majority circuit executes a majority operation on the outputs of the D/A converters to determine the broken D/A converter(s). The selector selects the output of well-behaved one of D/A converters.
Briefly, an object of the present invention is to provide an improved majority circuit, especially suitable for a memory device adopting a data inversion technology.
In detail, an object of the present invention is to reduce a size of a majority circuit.
Another object of the present invention is to reduce power consumption of a majority circuit.
Still another object of the present invention is to improve an operation speed of a majority circuit.
In an aspect of the present invention, a majority circuit is composed of a D/A converter converting a plurality of binary signals to an analogue signal, and a majority determining circuit responsive to the analogue signal to achieve a majority operation on the plurality of binary signals to produce a result signal representative of a result of the majority operation. The use of the D/A converter, which requires a reduced number of components, effectively reduces the size of the majority circuit.
The majority determining circuit preferably includes a reference signal generator generating a reference signal representative of a threshold of the majority operation, and a differential amplifier responsive to the analogue signal and the reference signal to develop the result signal.
The D/A converter may include a load resistor connected to a node, and a plurality of input transistors each connected to the node, the plurality of input transistors being responsive to the plurality of binary signals, respectively, for allowing currents to flow therethrough to develop the analogue signal on the node.
To reduce power consumption of the majority circuit, the D/A converter preferably includes a switching element which enables a current through the load resistor in response to an enable signal.
The reference signal generator may include a reference load resistor connected to a reference node, and a reference transistor connected to the reference node, the reference transistor allowing a reference current to flow therethrough to develop the reference signal on the reference node.
To reduce power consumption of the reference signal generator, the reference signal generator preferably includes a switching element which enables a current through the reference load resistor in response to an enable signal.
It is advantageous that the D/A converter further includes a plurality of first current mirror transistors respectively connected in series to the input transistors, the reference signal generator further includes a second current mirror transistor connected in series to the reference transistor, and the majority circuit further includes a bias circuit which provides a bias for each of the plurality of first current mirror transistors and the second current mirror transistor to control currents through the plurality of first current mirror transistors and the second current mirror transistors.
In the event that the bias circuit includes a bias transistor which forms a first current mirror with the plurality of first current mirror transistors, and forms a second current mirror with the second current mirror transistor, it is advantageous that a current mirror ratio of the second current mirror is 1/k times as large as a current mirror ratio of the first current mirror, the k being larger than 1, and a resistance of the reference load resistor is k times as large as a resistance of the load resistor within the D/A converter.
To improve operation speed of the majority circuit, it is preferable that the majority circuit further includes a precharge switching element between first and second inputs of the differential amplifier, respectively receiving the analogue signal and the reference signal, the precharge switching element being turned on to short-circuit the first and second inputs before the differential amplifier is enabled.
It is also preferable that the D/A converter includes a precharge control circuit which regulates a level of the analogue signal to that of the reference signal before the differential amplifier is enabled.
To increase the operation margin of the differential amplifier, the reference circuit preferably includes another D/A converter which receives complimentary input signals complimentary to the plurality of binary signals to output the reference signal so that the reference signal is complimentary to the analogue signal. In this case, the majority circuit preferably includes a resistor element disposed between first and second inputs of the differential amplifier, respectively receiving the analogue signal and the reference signal.
The reference circuit may include a first and second resistor elements connected in series between a power source supply and an earth terminal, and a reference node disposed between the first and second resistor, the reference signal being developed on the reference node.
The reference signal may be generated by an internal power source integrated within a same semiconductor within which the majority circuit is integrated.
To improve the operation speed of the majority circuit, the D/A converter preferably include a node on which the analogue signal is developed, a plurality of first input transistors for pulling up the node in response to the plurality of binary signals, respectively, and a plurality of second input transistors for pulling down the node in response to the plurality of binary signals, respectively.
In this case, the reference signal generator preferably includes a reference node on which the reference signal is developed, a plurality of first reference transistors for pulling up the reference node in response to a plurality of complimentary signals complimentary to the plurality of binary signals, respectively, and a plurality of second reference transistors for pulling down the reference node in response to the plurality of complimentary signals, respectively.
It is advantageous that the D/A converter further includes a plurality of first current mirror transistors connected in series to the plurality of first input transistors, respectively, and a plurality of second current mirror transistors connected in series to the plurality of second input transistors, respectively, and the majority circuit further includes a bias circuit which provides a first bias for the plurality of first current mirror transistors and a second bias for the plurality of second current mirror transistors so that currents through the plurality of first current mirror transistors are identical to currents through the plurality of second current mirror transistors.
In this case, the reference signal generator preferably includes a reference node on which the reference signal is developed, a plurality of first reference transistors for pulling up the reference node in response to a plurality of complimentary signals complimentary to the plurality of binary signals, respectively, and a plurality of second reference transistors for pulling down the reference node in response to the plurality of complimentary signals, respectively, a plurality of third current mirror transistors connected in series to the plurality of first reference transistors, respectively, and a plurality of fourth current mirror transistors connected in series to the plurality of second reference transistors, respectively, the bias circuit providing the first bias for the plurality of third current mirror transistors, and the second bias for the plurality of fourth current mirror transistors so that currents through the plurality of third and fourth current mirror transistors are identical to the currents through the plurality of first and second current mirror transistors.